A system-on-a-chip (SoC) often contains multiple masters requiring dynamic random-access memory (DRAM) access. These masters may include but are not limited to the following: Central Processing Units (CPUs), Digital Signal Processing units (DSPs), Graphics Processing Units (GPUs), Network Processing Units (NPUs), Direct Memory Access (DMA) controllers, 3D graphics accelerators, networking controllers, cache controllers, and wireless modems.
In a conventional SoC, the different masters are connected to the DRAM through an on-chip interconnect and a DRAM memory controller. In SoCs of this type, there is typically a high-level power control module that can recognize if the system is in a low-power mode or in a high-power mode, and a low-level power control that can recognize gaps in intermittent traffic and activate low-power modes (e.g. standby, nap, sleep, powerdown . . . etc) during inactivity.
Another important characteristic of a SoC is that not every master in the system has the same priority level. For example, CPUs typically have the highest priority in the system and require service within a few hundreds of nanoseconds. Some other masters may be very low-priority and may be delayed arbitrarily for tens of millions of nanoseconds as long as their requests are serviced within their maximum service time.
In order to reduce DRAM power usage, the DRAM should spend as much time as possible in its low-power modes. However, the DRAM typically uses more power than is necessary by executing all commands before entering the low-power mode. Often times, this provides no performance benefit to the SoC.
Accordingly, what is desired is to provide a system and method that overcomes the above issues. The present invention addresses such a need.